diff --git a/src/cpu/logic.rs b/src/cpu/logic.rs
index 8800084f80085ea79bc455005fd99bebb6e27322..ee1fe7dc5ca596922d26c776c3eb5505636927d4 100644
--- a/src/cpu/logic.rs
+++ b/src/cpu/logic.rs
@@ -21,4 +21,8 @@ impl CPU {
         }
         (&mut self.memory).store_instructions(instructions)
     }
+
+    pub fn free(&mut self) -> MSLResult<()> {
+        (&mut self.memory).free()
+    }
 }
diff --git a/src/main.rs b/src/main.rs
index 7cd6f7efeb44759cff0a6b20a545e952d88bb64e..75669bc04c6d2d0694b044821f6b018e57ad85c1 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -98,6 +98,7 @@ fn main() -> MSLResult<()> {
     } else {
         repl::start_repl_session()?;
     }
+    cpu.free()?;
     Ok(())
     //    println!("{:#?}", opt);
 }
diff --git a/src/ram/logic.rs b/src/ram/logic.rs
index 7b43fb53052d388043e38c6d77600dbc0c13ce12..81d199d3ea6610f30e3a476786d3c51c08cb5b73 100644
--- a/src/ram/logic.rs
+++ b/src/ram/logic.rs
@@ -32,6 +32,7 @@ impl RAM {
     ) -> MSLResult<()> {
         if address < self.mem.len() {
             self.mem[address] = data;
+            debug!("Data stored in RAM 0x{}", address);
             Ok(())
         } else {
             Err(MSLError::MemoryError(format!(
@@ -43,9 +44,23 @@ impl RAM {
     }
 
     pub fn store_instructions(&mut self, instructions: Vec<Instruction>) -> MSLResult<()> {
+        let instruction_len = instructions.len();
         for (i, item) in instructions.into_iter().enumerate() {
             self.store_data(i, RamValue::INSTR(item))?;
         }
+        debug!("{} instructions was loaded into RAM.", instruction_len);
+        Ok(())
+    }
+
+    pub fn free(&mut self) -> MSLResult<()> {
+        let freed = self.mem.iter().filter_map(|x| {
+            if RamValue::EMPTY == *x {
+                None
+            } else {
+                Some(RamValue::EMPTY)
+            }
+        }).collect::<Vec<_>>().len();
+        debug!("{} cells of RAM was freed.", freed);
         Ok(())
     }
 }